1. Field of the Invention
The present invention relates to a layout generating apparatus and a layout generating method of a semiconductor integrated circuit, as well as a program for directing a computer to execute the method.
2. Description of the Background Art
In designing semiconductor integrated circuits, there is increasing demand for improvements in the degree of integration, operation speed and power consumption of the circuits, whereas there is increasing demand for a reduction in design period. It is therefore required to improve the degree of integration, operation speed and power consumption in a short period of time.
As technique of increasing the efficiency of and automatizing the layout designs of semiconductor integrated circuits, there are, for example, a method called xe2x80x9clayout synthesisxe2x80x9d to generate a layout based on a net list (i.e., a connected information of transistor level), and a method called xe2x80x9ctechnology migrationxe2x80x9d to generate a layout of a desired design rule by using a layout drawn under a certain design rule.
When employing these techniques, it is desirable that the channel width of each transistor is optimized in designing a circuit, in order to improve the degree of integration, operation speed and power consumption of the circuit.
Referring now to the flowchart shown in FIG. 22, a procedure of generating a layout according to a conventional layout generating method will be described below.
First, in step S110, the data of a net list stored in memory is inputted, as an input data, to an optimization processing part that optimizes channel widths.
The optimization processing part optimizes a channel width to improve operation speed and reduce power consumption (step S111).
Specifically, the layout area is smaller as the transistor is smaller. In terms of improvements in the degree of integration, a smaller transistor is preferred, however, its operation speed cannot be increased. Also, power consumption might increase by through current due to blunting of waveform. It is therefore necessary to increase the size of a transistor that drives the portions requiring operation speed and the locations subjected to a large blunting of waveform.
Thus, the channel width optimization means to seek a transistor that should have a large channel width, and increase its channel width.
There are a variety of methods for optimizing the channel width of a transistor. One of the methods comprises the steps of: making a net list on which channel widths are minimized; seeking a transistor most contributing to improvements in driving speed and power consumption; and changing the channel width of the transistor. The sequence of these steps is repeated until a desired driving speed is attained.
Other method comprises the steps of allocating a certain value to all of the channel widths of transistors; and performing their respective simulations to obtain a combination of channel widths that produces the best result, as an optimum value.
In any case, when performing optimization, an upper limit value (the maximum value) of the channel width is set to avoid a reduction in the degree of integration of layout. Unless the maximum value is set, by the presence of a transistor occupying a large ratio of the layout area and exerting influence on operation speed and power consumption, the size of this transistor increases infinitely, resulting in a large layout area.
Returning to FIG. 22, in step S112, the net list obtained by optimizing the channel widths is temporarily stored in memory. A layout generation processing part generates a layout based on this net list (step S113).
This layout is then outputted and the sequence of the layout generation processing is completed (step S114).
The problems of the foregoing conventional techniques will be described by referring to FIG. 23 illustrating a buffer layout.
FIG. 23 illustrates the layout of a buffer formed by two CMOS inverters. In FIG. 23, an active area 21 where a P channel MOS transistor (PMOS transistor) is to be formed is disposed on the upper side, and an active area 31 where an N channel MOS transistor AMOS transistor) is to be formed is disposed on the lower side.
Gate electrodes 22 and 23 are placed in parallel on the active area 21. The portions of the active area 21, which locate at the side exterior in the longitudinal direction of the gate electrodes 22 and 23, become source/drain regions. Each of the source/drain regions is connected via a plurality of contact portions to an overlying first layer metal wiring 41. The portions of the active area 21, which underlie the gate electrodes 22 and 23, become channel regions.
Likewise, gate electrodes 32 and 33 are placed in parallel on the active area 31. The portions of the active area 31, which locate at the side exterior in the longitudinal direction of the gate electrodes 32 and 33, become source/drain regions. Each of the sour/drain region is connected via a plurality of contact portions to the overlying first layer metal wiring 41. The portions of the active area 31, which underlie the gate electrodes 32 and 33, become channel regions.
Referring to FIG. 23, when considering the two PMOS transistors on the active area 21, it is found that the gate electrode 22 is shorter than the gate electrode 23, and these electrodes have different channel widths. This is due to the connection constraint with the first layer metal wiring 41 and other wiring (not shown), by which the upper limit value of the channel widths on this circuit is determined. In general, the upper limit value of a channel width is more lowered at more complicated wiring location.
With the conventional layout generating method, the upper limit value of a channel width is set in the channel width optimization, however, this value is given as a whole. For example, an upper limit is set circuit by circuit. Actually, depending on the layout shape, the upper limit of a channel width is different transistor by transistor, as previously described. Therefore, the conventional techniques cannot accurately provide the upper limit value of a channel width at the time of optimization.
For instance, in FIG. 23, of the two PMOS transistors in the active area 21, the right transistor, as viewed in the figure, has room for increasing its channel width. Of the two NMOS transistors in the active area 31, the right transistor, as viewed in the figure, has room for increasing its channel width.
When a layout is generated setting an upper limit to a large value, the layout area is increased. On the contrary, setting the upper limit to a small value decreases the degree of freedom of optimization, which causes the degradation of optimization (i.e., a drop in operation speed and an increase in power consumption on circuit).
According to a first aspect of the invention, a layout generating apparatus to generate a layout of a semiconductor integrated circuit comprises: a compaction processing part to perform a compaction processing for converting an inputted input layout into a layout satisfying a predetermined design rule; and a channel-width optimization processing part to optimize a channel width of a transistor forming the semiconductor integrated circuit, the compaction processing part having a channel-width maximization processing part that maximizes the channel width of the transistor without changing a layout area to generate a layout after channel-width maximization and obtain a maximum channel-width value, the channel-width optimization processing part optimizing the channel width of the transistor by using the maximum channel-width value as an upper limit value.
According to a second aspect of the invention, the layout generating apparatus of the first aspect is characterized in that the compaction processing part further has a channel-width minimization processing part that minimizes the channel width of the transistor without changing a layout area to generate a layout after channel-width minimization and obtain a minimum channel-width value, the channel-width optimization processing part optimizing the channel width of the transistor by using the maximum channel-width value as an upper limit value and the minimum channel-width value as a lower limit value.
According to a third aspect of the invention, the layout generating apparatus of the first aspect further comprises a parasitic capacity/resistance sampling processing part to obtain a parasitic capacity and a resistance value of wiring of the transistor based on the layout after channel-width maximization, wherein the channel-width optimization processing part optimizes the channel width of the transistor on receipt of data of the parasitic capacity and the resistance value.
According to a fourth aspect of the invention, the layout generating apparatus of the first aspect is characterized in that the input layout is a temporal layout generated based on a net list data.
According to a fifth aspect of the invention, the layout generating apparatus of the first aspect is characterized in that the input layout is obtained by subjecting a layout generated under a design rule different from the predetermined design rule, to a preprocessing in a technology migration processing.
According to a sixth aspect of the invention, a layout generating method of generating a layout of a semiconductor integrated circuit comprises the steps of: (a) performing a compaction processing for converting an inputted input layout into a layout satisfying a predetermined design rule; and (b) optimizing the channel width of a transistor forming the semiconductor integrated circuit, the step (a) including: (a-1) maximizing the channel width of the transistor without changing a layout area to obtain a layout after channel-width maximization; and (a-2) obtaining a maximum channel-width value from the layout after channel-width maximization, the step (b) including the step of optimizing the channel width of the transistor by using the maximum channel-width value as an upper limit value.
According to a seventh aspect of the invention, the layout generating method of the sixth aspect is characterized in that the step (a) further includes: (a-3) minimizing the channel width of the transistor without changing a layout area to obtain a layout after channel-width minimization; and (a-4) obtaining a minimum channel-width value from the layout after channel-width minimization, the step (b) including the step of optimizing the channel width of the transistor by using the maximum channel-width value as an upper limit value and the minimum channel-width value as a lower limit value.
According to an eighth aspect of the invention, the layout generating method of the sixth aspect further comprises the step (c), prior to the step (b), of obtaining a parasitic capacity and a resistance value of wiring of the transistor based on the layout after channel-width maximization, the step (b) including the step of optimizing the channel width of the transistor on receipt of data of the parasitic capacity and the resistance value.
According to a ninth aspect of the invention, the layout generating method of the sixth aspect is characterized in that the input layout is generated as a temporal layout, prior to the step (a) and based on a net list data.
According to a tenth aspect of the invention, the layout generating method of the sixth aspect is characterized in that the input layout is obtained, prior to the step (a), by subjecting a layout generated under a design rule different from the predetermined design rule, to a preprocessing in a technology migration processing.
According to an eleventh aspect of the invention, a program for directing a computer to execute the layout generating method of the sixth aspect.
In the layout generating apparatus of the first aspect, the compaction processing part has the channel-width maximization processing part that maximizes the channel width of a transistor without changing the layout area to generate a layout after channel-width maximization, and obtains a maximum channel-width value. The channel-width optimization processing part optimizes the channel width of the transistor by using the maximum channel-width value as an upper limit value. Therefore, a layout having a channel width optimized based on the layout constraint can be obtained per transistor. Since an optimum channel width is obtained based on the result of such an optimization processing that a channel width is maximized without changing the layout area, a larger channel width can be obtained, thereby increasing the operation speed of the semiconductor integrated circuit. In addition, setting the condition so as to satisfy the operation speed constraint does not unnecessarily increase the channel width of a transistor involving an increase in layout area but increases the channel width of a transistor causing no increase in layout area, thus permitting an increase in operation speed. As a result, the layout area can be reduced to increase the degree of freedom of channel width selection, which increases the degree of freedom of optimization and allows for a reduction in power consumption.
In the layout generating apparatus of the second aspect, the compaction processing part further has the channel-width minimization processing part that minimizes the channel width of a transistor without changing the layout area, to generate a layout after channel-width minimization and obtains a minimum channel-width value. The channel-width optimization processing part optimizes the channel width of the transistor by using the maximum channel-width value as an upper limit value and the minimum channel-width value as a lower limit value. Therefore, a layout having a channel width optimized more accurately based on the layout constraint can be obtained per transistor. As a result, there is no possibility that an excessive reduction of channel width causes a decrease or an increase in layout area, thus failing to achieve the target layout area. This avoids elongating of the design period necessary for correction.
The layout generating apparatus of the third aspect further comprises the parasitic capacity/resistance sampling processing part to obtain the parasitic capacity and resistance value of the wiring of the transistor based on a layout after channel-width maximization. Therefore, the channel width is optimized not only based on the layout constraint but also in consideration of the resistance value and parasitic capacity of the wiring, thereby obtaining the channel-width optimization result of high reliability. As a result, there is no possibility of failing to obtain a desired characteristic due to a channel-width optimization processing of low reliability. This avoids elongating of the design period necessary for correction.
In the layout generating apparatus of the fourth aspect, an input layout is a temporal layout generated based on a net list data, and the so-called layout synthesis processing generates the input layout. Therefore, a variety of design rules can be used and there can be provided a flexible operation, for example, the layout shape to be outputted can be controlled to a certain degree.
In the layout generating apparatus of the fifth aspect, an input layout is obtained by subjecting a layout generated under a design rule different from a predetermined design rule to a preprocessing in the technology migration. Therefore, the design period can be made shorter than the layout synthesis processing of generating a layout from a net list.
With the layout generating method of the sixth aspect, in the step (a-1), a layout after channel-width maximization is generated by maximizing the channel width of a transistor without changing the layout area; in the step (a-2), a maximum channel-width value is obtained from the layer after channel-width maximization; and in the step (b), the channel width of the transistor is optimized by using the maximum channel-width value as an upper limit value. Therefore, a layout having a channel width optimized based on the layout constraint can be obtained per transistor. Since an optimum channel width is obtained based on the result of such an optimization processing that a channel width is maximized without changing the layout area, a larger channel width can be obtained, thereby increasing the operation speed of the semiconductor integrated circuit. In addition, setting the condition so as to satisfy the operation speed constraint does not unnecessarily increase the channel width of a transistor involving an increase in layout area but increases the channel width of a transistor causing no increase in layout area, thus permitting an increase in operation speed. As a result, the layout area can be reduced to increase the degree of freedom of channel width selection, which increases the degree of freedom of optimization and allows for a reduction in power consumption.
With the layout generating method of the seventh aspect, in the step (a-3), a layout after channel-width minimization is generated by minimizing the channel width of a transistor without changing the layout area; in the step (a-4), a minimum channel-width value is obtained from the layout after channel-width minimization; and in the step (b), the channel width of the transistor is optimized by using the maximum channel-width value as an upper limit value and the minimum channel-width value as a lower limit value. Therefore, a layout having a channel width optimized more accurately based on the layout constraint can be obtained per transistor. As a result, there is no possibility that an excessive reduction of channel width causes a decrease or an increase in layout area, thus failing to achieve the target layout area. This avoids elongating of the design period necessary for correction.
With the layout generating method of the eighth aspect, in the step (c), the parasitic capacity and resistance value of wiring of the transistor are obtained based on the layout after channel-width maximization; in step (b), the channel width of the transistor is optimized on receipt of the data of the parasitic capacity and resistance value. Therefore, the channel width is optimized not only based on the layout constraint but also in consideration of the resistance value and parasitic capacity of the wiring, thereby obtaining the channel-width optimization result of high reliability. As a result, there is no possibility of failing to obtain a desired characteristic due to a channel-width optimization processing of low reliability. This avoids elongating of the design period necessary for correction.
With the layout generating method of the ninth aspect, the so-called layout synthesis processing generates an input layout. Therefore, a variety of design rules can be used, and there can be provided a flexible operation, for example, the layout shape to be outputted can be controlled to a certain degree.
With the layout generating method of the tenth aspect, the design period can be made shorter than the layout synthesis processing of generating a layout from a net list.
With the eleventh aspect, a layout having a channel width optimized based on the layout constraint can be obtained by executing the program.
It is an object of the present invention to overcome the foregoing problems by providing a layout generating apparatus and a layout generating method to obtain high-quality optimization results (improvements in operation speed and in the degree of integration and a reduction in power consumption).
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.